Implementation of RISC System in FPGA
نویسندگان
چکیده
This paper represents the combination of Reduced Instruction Set Computer (RISC) system using VHDL and implement. This paper presents a RISC processor designing to achieve various arithmetic operations. The RISC is a 20 bit processor. KeywordsArithmetic Logic(AL), Central Processing Unit(CPU), Control Unit(CU), Field Programmable Logic Array(FPGA), General Purpose Register(GPR), Program Counter(PC) Instruction Register(IR), , Reduced Instruction Set Computer(RISC), Register Set(RS), Configurable Logic Blocks (CLBs)
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